Field of the Invention
This invention relates generally to analog-to-digital (A/D) converters and, more particularly, to a metal-oxide-semiconductor (MOS) charge-redistribution, successive-approximation analog-to-digital converter which is simple, occupies little silicon area and which reduces errors due to comparator input leakage problems.
The advantages offered by NMOS technology are well known; e.g. higher density, greater yield, etc. Thus, smaller NMOS device geometries permit a greater number of devices to be produced per unit area or, stated another way, a single NMOS device will occupy less space. This characteristic is extremely important in the design and fabrication of complex digital integrated circuits; for example, single chip microprocessors.
Whereas digital circuitry is generally characterized by its "on/off" or "one/zero" nature, most measurements in the real world are inherently analog; e.g. temperature, pressure, speed, voltage, etc. Therefore, it is necessary that microprocessors and other digital circuitry communicate or interface with analog circuitry such as amplifiers, buffers, comparators, etc., in order to permit digital processing of analog signals. In each case, it is also necessary to convert the analog signals to digital voltage levels.
The required interfacing between digital and analog circuitry may be accomplished by providing analog components which are external to the microprocessor chip. However, such arrangements generally are more expensive, require more current, a larger power supply and commonly present more opportunities for design and manufacturing errors. To avoid these disadvantages, complex analog circuits such as A/D converters are being manufactured integrally with the digital circuitry; eg. on the microprocessor chip itself, and due to the complex nature of microprocessors, the inclusion of analog devices on the same chip requires that the same manufacturing process be employed. Thus, an A/D converter included on an NMOS microprocessor chip must be fabricated in accordance with NMOS processing techniques, and the design of the analog circuits such as A/D converter circuits must be tailored to such processing techniques.
Successive approximation analog-to-digital conversion is well known. For example, see U.S. Pat. Nos. 3,964,061; 3,949,395; 3,603,970; and 3,581,304. It involves the repeated division of the voltage range in half. In a three bit system, for example, the system will first try 100 (half scale). Next, the system will try 010 (quarter scale) or 110 (three-quarter scale) depending on whether the first approximation was too large or too small. After three approximations, a three bit representation of the unknown analog voltage is resolved. A discussion of successive-approximation A/D converters may be found in Integrated Electronics: Analog and Digital Circuits and Systems, McGraw-Hill, Inc., 1972, page 667.
It is also known to use a sample-and-hold circuit in conjunction with an A/D converter. A capacitor (or capacitors) is charged with the unknown analog input voltage during a sample phase, and retains the value during the conversion phase. The holding time is the length of time the circuit can hold a charge without dropping more than a specified percentage of its initial value. For an additional discussion of such circuits, see The Logic Handbook, Digital Equipment Corporation, 1967 Edition, page 281.
Charge redistribution approaches to A/D conversion are known e.g. U.S. Pat. No. 4,065,766. Further, the use of binary weighted capacitors is known; e.g. U.S. Pat. No. 3,836,906. In one known A/D conversion arrangement, a plurality of binary weighted capacitors are each charged by an unknown analog input signal. The common output of each of the capacitors is coupled to the input of a chopper stabilized comparator (a plurality of inverters each separated by a capacitor) which, during the sample phase, is caused to assume an input voltage which is right at its threshold voltage; i.e., a small variation at its input will cause the comparator to switch. After the sample phase, the input to the comparator is left floating; i.e. no d.c. paths. Thereafter, signals from a successive approximation register are used to control a plurality of field-effect-transistor (FET) couplers to couple each of the binary weighted capacitors to either the high reference voltage (VRH) typically 5 volts in an NMOS system or to a low reference voltage (VRL) typically ground. The analog input voltage, which may also be as high as VRH, requires field-effect-transistor coupling to each of the capacitors. It should be appreciated, that to pass either the analog input voltage or the high reference voltage through the various coupling field-effect-transistor coupling switches, it is necessary that the enabling voltage placed on the gate electrodes of the field-effect-transistor couplers be higher than the sum of the voltage being passed plus the FET threshold voltage. In a system in which the analog input voltage may be as high as the circuit supply voltage (typically 5 volts), a voltage boost circuit would be required in each case to achieve the required gate electrode voltages.
A second problem associated with the known circuit resides in the fact that a field-effect-transistor coupler has its current conducting path connected across the input and output of the comparator. When the high reference voltage is 5 volts and the low reference voltage is zero volts, and assuming an unknown analog input signal of 5 volts, the balanced comparator input node voltage (the comparator threshold voltage) is typically 2 volts or less. Sampling is done on all binary weighted capacitors, and the first approximation connects all but the largest capacitor to ground. That is, the first approximation is 2.5 volts. Assuming negligible attenuation through the capacitors, the resulting redistribution of charge causes the comparator input voltage to drop by 2.5 volts (the analog input voltage minus the first approximation voltage), resulting in a net voltage at the input of the comparator of -0.5 volts. This, however, tends to turn on the field-effect-transistor coupler across the first stage of the comparator causing leakage to occur at the comparator input node. Since the charge stored on this node is in essence the stored sample, accuracy is lost. One known technique for avoiding this effect is to deliberately increase the parasitic capacitance at the comparator input. This, however, greatly reduces the sensitivity of the comparator and also requires more silicon area.